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? 2009 microchip technology inc. ds39896b pic18f6393/6493/8393/8493 data sheet 64/80-pin high performance, flash microcontrollers with lcd driver, 12-bit adc and nanowatt technology
ds39896b-page 2 ? 2009 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, octopus, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, pic 32 logo, real ice, rflab, select mode, total endurance, tsharc, uniwin driver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2009 microchip technology inc. ds39896b-page 3 pic18f6393/6493/8393/8493 lcd driver module features: ? direct driving of lcd panel ? up to 192 pixels: software selectable ? programmable lcd timing module: - multiple lcd timing sources available - up to four commons: static, 1/2, 1/3 or 1/4 multiplex - static, 1/2 or 1/3 bias configuration ? can drive lcd panel while in sleep mode for low-power operation power-managed modes: ? run: cpu on, peripherals on ? idle: cpu off, peripherals on ? sleep: cpu off, peripherals off ? run mode current down to 14 a typical ? idle mode currents down to 5.8 a typical ? sleep mode currents down to 0.1 a typical ? timer1 oscillator: 1.8 a, 32 khz, 2v ? watchdog timer: 2.1 a typical ? two-speed oscillator start-up flexible oscillator structure: ? four crystal modes: - lp: up to 200 khz - xt: up to 4 mhz - hs: up to 40 mhz - hspll: 4-10 mhz (16-40 mhz internal) ? 4x phase lock loop (available for crystal and internal oscillators) ? two external rc modes, up to 4 mhz ? two external clock modes, up to 40 mhz ? internal oscillator block: - eight selectable frequencies, from 31 khz to 8 mhz - provides a complete range of clock speeds from 31 khz to 32 mhz when used with pll - user-tunable to compensate for frequency drift ? secondary oscillator using timer1 at 32 khz ? fail-safe clock monitor: - allows for safe shutdown of device if primary or secondary clock fails peripheral highlights: ? 12-bit, up to 12-channel analog-to-digital (a/d) converter module: - auto-acquisition capability - conversion available during sleep ? high-current sink/source 25 ma/25 ma ? four external interrupts ? four input change interrupts ? four 8-bit/16-bit timer/counter modules ? real-time clock (rtc) software module: - configurable 24-hour clock, calendar, automatic 100-year or 12,800-year, day-of-week calculator - uses timer1 ? up to two capture/compare/pwm (ccp) modules ? master synchronous serial port (mssp) module supporting three-wire spi (all four modes) and i 2 c? master and slave modes ? addressable usart module: - supports rs-485 and rs-232 ? enhanced addressable usart module: - supports rs-485, rs-232 and lin 1.2 - auto-wake-up on start bit - auto-baud detect ? dual analog comparators with input multiplexing special microcontroller features: ? c compiler optimized architecture: - optional extended instruction set designed to optimize re-entrant code ? 1000 erase/write cycle flash program memory typical ? flash retention: 100 years typical ? priority levels for interrupts ? 8 x 8 single-cycle hardware multiplier ? extended watchdog timer (wdt): - programmable period from 4 ms to 132s - 2% stability over v dd and temperature ? in-circuit serial programming? (icsp?) via two pins ? in-circuit debug (icd) via two pins ? wide operating voltage range: 2.0v to 5.5v note: this document is supplemented by the ? pic18f6390/6490/8390/8490 data sheet? (ds39629). see section 1.0 ?device overview? . 64/80-pin high-performance, flash microcontrollers with lcd driver, 12-bit adc and nanowatt technology
pic18f6393/6493/8393/8493 ds39896b-page 4 ? 2009 microchip technology inc. pin diagrams device program memory data memory i/o lcd (pixel) 12-bit a/d (channels) ccp (pwm) mssp eusart/ ausart comparators timers 8/16-bit flash (bytes) # single-word instructions sram (bytes) spi master i 2 c? pic18f6393 8k 4096 768 50 128 12 2 y y 1/1 2 1/3 PIC18F6493 16k 8192 768 50 128 12 2 y y 1/1 2 1/3 pic18f8393 8k 4096 768 66 192 12 2 y y 1/1 2 1/3 pic18f8493 16k 8192 768 66 192 12 2 y y 1/1 2 1/3 64-pin tqfp note 1: re7 is the alternate pin for ccp2 multiplexing . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 38 37 36 35 34 33 50 49 17 18 19 20 21 22 23 24 25 26 lcdbias3 com0 re4/com1 re5/com2 re6/com3 re7/ccp2 (1) /seg31 rd0/seg0 v dd v ss rd1/seg1 rd2/seg2 rd3/seg3 rd4/seg4 rd5/seg5 rd6/seg6 rd7/seg7 lcdbias2 lcdbias1 rg0/seg30 rg1/tx2/ck2/seg29 rg2/rx2/dt2/seg28 rg3/seg27 mclr /v pp /rg5 rg4/seg26 v ss v dd rf7/ss /seg25 rf6/an11/seg24 rf5/an10/cv ref /seg23 rf4/an9/seg22 rf3/an8/seg21 rf2/an7/c1out/seg20 rb0/int0 rb1/int1/seg8 rb2/int2/seg9 rb3/int3/seg10 rb4/kbi0/seg11 rb5/kbi1 rb6/kbi2/pgc v ss osc2/clko/ra6 osc1/clki/ra7 v dd rb7/kbi3/pgd rc4/sdi/sda rc3/sck/scl rc2/ccp1/seg13 rf0/an5/seg18 rf1/an6/c2out/seg19 av dd av ss ra3/an3/v ref +/seg17 ra2/an2/v ref -/seg16 ra1/an1 ra0/an0 v ss v dd ra4/t0cki/seg14 ra5/an4/hlvdin/seg15 rc1/t1osi/ccp2 (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 rc5/sdo/seg12 15 16 31 40 39 27 28 29 30 32 48 47 46 45 44 43 42 41 54 53 52 51 58 57 56 55 60 59 64 63 62 61 pic18f6393 PIC18F6493
? 2009 microchip technology inc. ds39896b-page 5 pic18f6393/6493/8393/8493 pin diagrams (continued ) 80-pin tqfp note 1: re7 is the alternate pin for ccp2 multiplexing . 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 lcdbias3 com0 re4/com1 re5/com2 re6/com3 re7/ccp2 (1) /seg31 rd0/seg0 v dd v ss rd1/seg1 rd2/seg2 rd3/seg3 rd4/seg4 rd5/seg5 rd6/seg6 rd7/seg7 lcdbias2 lcdbias1 rg0/seg30 rg1/tx2/ck2/seg29 rg2/rx2/dt2/seg28 rg3/seg27 mclr /v pp /rg5 rg4/seg26 v ss v dd rf7/ss /seg25 rb0/int0 rb1/int1/seg8 rb2/int2/seg9 rb3/int3/seg10 rb4/kbi0/seg11 rb5/kbi1 rb6/kbi2/pgc v ss osc2/clko/ra6 osc1/clki/ra7 v dd rb7/kbi3/pgd rc4/sdi/sda rc3/sck/scl rc2/ccp1/seg13 rf0/an5/seg18 rf1/an6/c2out/seg19 av dd av ss ra3/an3/v ref +/seg17 ra2/an2/v ref -/seg16 ra1/an1 ra0/an0 v ss v dd ra4/t0cki/seg14 ra5/an4/hlvdin/seg15 rc1/t1osi/ccp2 (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 rc5/sdo/seg12 rj0/seg32 rj1/seg33 rh1/seg46 rh0/seg47 1 2 rh2/seg45 rh3/seg44 17 18 rh7/seg43 rh6/seg42 rh5/seg41 rh4/seg40 rj5/seg38 rj4/seg39 37 rj7/seg36 rj6/seg37 50 49 rj2/seg34 rj3/seg35 19 20 33 34 35 36 38 58 57 56 55 54 53 52 51 60 59 68 67 66 65 72 71 70 69 74 73 78 77 76 75 79 80 rf5/an10/cv ref /seg23 rf4/an9/seg22 rf3/an8/seg21 rf2/an7/c1out/seg20 rf6/an11/seg24 pic18f8393 pic18f8493
pic18f6393/6493/8393/8493 ds39896b-page 6 ? 2009 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 9 2.0 12-bit analog-to-digital converter (a/d) module ............................................................................. .......................................... 31 3.0 special features of the cpu ................................................................................................. ..................................................... 41 4.0 electrical characteristics ................................................................................................. .......................................................... 43 5.0 packaging information....................................................................................................... ......................................................... 47 appendix a: revision history................................................................................................... ............................................................ 49 appendix b: device differences................................................................................................. .......................................................... 49 appendix c: conversion considerations .......................................................................................... ................................................... 50 appendix d: migration from baseline to enhanced devices........................................................................ ........................................ 50 appendix e: migration from mid-range to enhanced devices ....................................................................... ..................................... 51 appendix f: migration from high-end to enhanced devices ........................................................................ ....................................... 51 the microchip web site ......................................................................................................... .............................................................. 55 customer change notification service ........................................................................................... ..................................................... 55 customer support ............................................................................................................... ................................................................. 55 reader response ................................................................................................................ ................................................................ 56 product identification system.................................................................................................. ............................................................. 57
? 2009 microchip technology inc. ds39896b-page 7 pic18f6393/6493/8393/8493 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
pic18f6393/6493/8393/8493 ds39896b-page 8 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds39896b-page 9 pic18f6393/6493/8393/8493 1.0 device overview this document contains device-specific information for the following devices: this family offers the advantages of all pic18 microcontrollers ? namely, high computational performance at an economical price. in addition to these features, the pic18f6393/6493/8393/8493 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power-sensitive applications. 1.1 special features ? 12-bit a/d converter: this module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduces code overhead. 1.2 details on individual family members devices in the pic18f6393/6493/8393/8493 family are available in 64-pin (pic18f6x93) and 80-pin (pic18f8x93) packages. block diagrams for the two groups are shown in figure 1-1 and figure 1-2, respectively. the devices are differentiated from each other in the following ways: ? i/o ports: - 64-pin devices ? 7 bidirectional ports - 80-pin devices ? 9 bidirectional ports ? lcd pixels: - 64-pin devices ? 128 (32 segs x 4 coms) pixels can be driven - 80-pin devices ? 192 (48 segs x 4 coms) pixels can be driven ? flash program memory: - pic18fx393 devices ? 8 kbytes - pic18fx493 devices ? 16 kbytes all other features for devices in this family are identical. these are summarized in table 1-1. the pinouts for all devices are listed in table 1-2 and table 1-3. like all microchip pic18 devices, members of the pic18f6393/6493/8393/8493 family are available as both standard and low-voltage devices. standard devices with flash memory, designated with an ?f? in the part number (such as pic18f6393), accommodate an operating v dd range of 4.2v to 5.5v. low-voltage parts, designated by ?lf? (such as pic18lf6490), function over an extended v dd range of 2.0v to 5.5v. ? pic18f6393 ? pic18f8393 ? PIC18F6493 ? pic18f8493 note: this data sheet documents only the devices? features and specifications that are in addition to the features and specifications of the pic18f6390/6490/8390/8490 devices. for information on the features and specifications shared by the pic18f6393/ 6493/8393/8493 and pic18f6390/6490/ 8390/8490 devices, see the ? pic18f6390/ 6490/8390/8490 data sheet? (ds39629).
pic18f6393/6493/8393/8493 ds39896b-page 10 ? 2009 microchip technology inc. table 1-1: device features features pic18f6393 PIC18F6493 pic18f8393 pic18f8493 operating frequency dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz program memory (bytes) 8k 16k 8k 16k program memory (instructions) 4096 8192 4096 8192 data memory (bytes) 768 768 768 768 interrupt sources 22 22 22 22 i/o ports ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g, h, j ports a, b, c, d, e, f, g, h, j number of pixels the lcd driver can drive 128 (32 segs x 4 coms) 128 (32 segs x 4 coms) 192 (48 segs x 4 coms) 192 (48 segs x 4 coms) timers 4444 capture/compare/pwm modules 2 2 2 2 serial communications mssp, ausart, enhanced usart mssp, ausart, enhanced usart mssp, ausart, enhanced usart mssp, ausart, enhanced usart 12-bit analog-to-digital module 12 input channels 12 input channels 12 input channels 12 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt programmable low-voltage detect yes yes yes yes programmable brown-out reset yes yes yes yes instruction set 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled packages 64-pin tqfp 64-pin tqfp 80-pin tqfp 80-pin tqfp
? 2009 microchip technology inc. ds39896b-page 11 pic18f6393/6493/8393/8493 figure 1-1: pic18f6x93 ( 64-pin) block diagram instruction decode and control porta portb portc ra4/t0cki/seg14 ra5/an4/hlvdin/seg15 rb0/int0 rc0/t1oso/t13cki rc1/t1osi/ccp2 (1) rc2/ccp1 /seg13 rc3/sck/scl rc4/sdi/sda rc5/sdo /seg12 rc6/tx1/ck1 rc7/rx1/dt1 ra3/an3/v ref +/seg17 ra2/an2/v ref -/seg16 ra1/an1 ra0/an0 rb1/int1/seg8 data latch data memory (3.9 kbytes) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> address latch program memory (48/64 kbytes) data latch 20 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 rb2/int2/seg9 rb3/int3/seg10 pclatu pcu portd rd7/seg7:rd0/seg0 osc2/clko (3) /ra6 note 1: ccp2 is multiplexed with rc1 when configuration bit, ccp2mx, is set, or re7 when ccp2mx is not set. 2: rg5 is only available when mclr functionality is disabled. 3: osc1/clki and osc2/clko are only available in select oscillator modes and when these pins are not being used as digital i/o. for additional information, see section 2.0 ?oscillator configurations? of the ? pic18f6390/6490/8390/8490 data sheet? (ds39629). rb4/kbi0/seg11 rb5/kbi1 rb6/kbi2/pgc rb7/kbi3/pgd eusart1 comparators mssp timer2 timer1 timer3 timer0 hlvd ccp1 bor adc 12-bit w instruction bus <16> stkptr bank 8 state machine control signals decode 8 8 power-up timer oscillator start-up timer power-on reset watchdog timer osc1 (3) osc2 (3) v dd , brown-out reset internal oscillator fail-safe clock monitor precision reference band gap v ss mclr (2) block intrc oscillator 8 mhz oscillator single-supply programming in-circuit debugger t1osi t1oso osc1/clki (3) /ra7 porte lcdbias1 lcdbias2 lcdbias3 com0 re4/com1 re5/com2 re6/com3 re7/ccp2 (1) /seg31 portf rf0/an5 /seg18 rf1/an6/c2out /seg19 rf2/an7/c1out /seg20 rf3/an8 /seg21 rf4/an9 /seg22 rf5/an10/cv ref /seg23 rf6/an11 /seg24 rf7/ss /seg25 portg rg0 /seg30 rg1/tx2/ck2 /seg29 rg2/rx2/dt2 /seg28 rg3 /seg27 rg4 /seg26 mclr /v pp /rg5 (2) ausart2 ccp2 lcd driver rom latch
pic18f6393/6493/8393/8493 ds39896b-page 12 ? 2009 microchip technology inc. figure 1-2: pic18f8x93 (80-pin) block diagram instruction decode and control data latch data memory (3.9 kbytes) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 412 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> address latch program memory (48/64 kbytes) data latch 20 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 rom latch pclatu pcu note 1: ccp2 is multiplexed with rc1 when configuration bit, ccp2mx, is set and re7 when ccp2mx is not set. 2: rg5 is only available when mclr functionality is disabled. 3: osc1/clki and osc2/clko are only available in select oscillator modes and when these pins are not being used as digital i/o. for additional information, see section 2.0 ?oscillator configurations? of the ? pic18f6390/6490/8390/8490 data sheet? (ds39629). eusart1 comparators mssp timer2 timer1 timer3 timer0 hlvd ccp1 bor adc 12-bit w instruction bus <16> stkptr bank 8 state machine control signals decode 8 8 power-up timer oscillator start-up timer power-on reset watchdog timer osc1 (3) osc2 (3) v dd , brown-out reset internal oscillator fail-safe clock monitor precision reference band gap v ss mclr (2) block intrc oscillator 8 mhz oscillator single-supply programming in-circuit debugger t1osi t1oso ausart2 ccp2 porth rh7/seg40:rh4/seg43 rh3/seg47:rh0/seg44 lcd driver porta portb portc ra4/t0cki/seg14 ra5/an4/hlvdin/seg15 rb0/int0 rc0/t1oso/t13cki rc1/t1osi/ccp2 (1) rc2/ccp1 /seg13 rc3/sck/scl rc4/sdi/sda rc5/sdo /seg12 rc6/tx1/ck1 rc7/rx1/dt1 ra3/an3/v ref +/seg17 ra2/an2/v ref -/seg16 ra1/an1 ra0/an0 rb1/int1/seg8 rb2/int2/seg9 rb3/int3/seg10 portd rd7/seg7:rd0/seg0 osc2/clko (3) /ra6 rb4/kbi0/seg11 rb5/kbi1 rb6/kbi2/pgc rb7/kbi3/pgd osc1/clki (3) /ra7 porte lcdbias1 lcdbias2 lcdbias3 com0 re4/com1 re5/com2 re6/com3 re7/ccp2 (1) /seg31 portf rf0/an5 /seg18 rf1/an6/c2out /seg19 rf2/an7/c1out /seg20 rf3/an8 /seg21 rf4/an9 /seg22 rf5/an10/cv ref /seg23 rf6/an11 /seg24 rf7/ss /seg25 portg rg0 /seg30 rg1/tx2/ck2 /seg29 rg2/rx2/dt2 /seg28 rg3 /seg27 rg4 /seg26 mclr /v pp /rg5 (2) portj rj7/seg36:rj4/seg39 rj3/seg35:rj0/seg32
? 2009 microchip technology inc. ds39896b-page 13 pic18f6393/6493/8393/8493 table 1-2: pic18f6x93 pi nout i/o descriptions pin name pin number pin type buffer type description tqfp mclr /v pp /rg5 mclr v pp rg5 7 i p i st st master clear (input) or programming voltage (input). master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. digital input. osc1/clki/ra7 osc1 clki ra7 39 i i i/o st cmos ttl oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode; cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 40 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f6393/6493/8393/8493 ds39896b-page 14 ? 2009 microchip technology inc. porta is a bidirectional i/o port. ra0/an0 ra0 an0 24 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 23 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref -/seg16 ra2 an2 v ref - seg16 22 i/o i i o ttl analog analog analog digital i/o. analog input 2. a/d reference voltage (low) input. seg16 output for lcd. ra3/an3/v ref +/seg17 ra3 an3 v ref + seg17 21 i/o i i o ttl analog analog analog digital i/o. analog input 3. a/d reference voltage (high) input. seg17 output for lcd. ra4/t0cki/seg14 ra4 t0cki seg14 28 i/o i o st/od st analog digital i/o. open-drain when configured as output. timer0 external clock input. seg14 output for lcd. ra5/an4/hlvdin/seg15 ra5 an4 hlvdin seg15 27 i/o i i o ttl analog analog analog digital i/o. analog input 4. low-voltage detect input. seg15 output for lcd. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. table 1-2: pic18f6x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39896b-page 15 pic18f6393/6493/8393/8493 portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0 rb0 int0 48 i/o i ttl st digital i/o. external interrupt 0. rb1/int1/seg8 rb1 int1 seg8 47 i/o i o ttl st analog digital i/o. external interrupt 1. seg8 output for lcd. rb2/int2/seg9 rb2 int2 seg9 46 i/o i o ttl st analog digital i/o. external interrupt 2. seg9 output for lcd. rb3/int3/seg10 rb3 int3 seg10 45 i/o i o ttl st analog digital i/o. external interrupt 3. seg10 output for lcd. rb4/kbi0/seg11 rb4 kbi0 seg11 44 i/o i o ttl ttl analog digital i/o. interrupt-on-change pin. seg11 output for lcd. rb5/kbi1 rb5 kbi1 43 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb6/kbi2/pgc rb6 kbi2 pgc 42 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 37 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-2: pic18f6x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f6393/6493/8393/8493 ds39896b-page 16 ? 2009 microchip technology inc. portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 30 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 (1) 29 i/o i i/o st cmos st digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm2 output. rc2/ccp1/seg13 rc2 ccp1 seg13 33 i/o i/o o st st analog digital i/o. capture 1 input/compare 1 output/pwm1 output. seg13 output for lcd. rc3/sck/scl rc3 sck scl 34 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi/sda rc4 sdi sda 35 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo/seg12 rc5 sdo seg12 36 i/o o o st ? analog digital i/o. spi data out. seg12 output for lcd. rc6/tx1/ck1 rc6 tx1 ck1 31 i/o o i/o st ? st digital i/o. eusart1 asynchronous transmit. eusart1 synchronous clock (see related rx1/dt1). rc7/rx1/dt1 rc7 rx1 dt1 32 i/o i i/o st st st digital i/o. eusart1 asynchronous receive. eusart1 synchronous data (see related tx1/ck1). table 1-2: pic18f6x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39896b-page 17 pic18f6393/6493/8393/8493 portd is a bidirectional i/o port. rd0/seg0 rd0 seg0 58 i/o o st analog digital i/o. seg0 output for lcd. rd1/seg1 rd1 seg1 55 i/o o st analog digital i/o. seg1 output for lcd. rd2/seg2 rd2 seg2 54 i/o o st analog digital i/o. seg2 output for lcd. rd3/seg3 rd3 seg3 53 i/o o st analog digital i/o. seg3 output for lcd. rd4/seg4 rd4 seg4 52 i/o o st analog digital i/o. seg4 output for lcd. rd5/seg5 rd5 seg5 51 i/o o st analog digital i/o. seg5 output for lcd. rd6/seg6 rd6 seg6 50 i/o o st analog digital i/o. seg6 output for lcd. rd7/seg7 rd7 seg7 49 i/o o st analog digital i/o. seg7 output for lcd. table 1-2: pic18f6x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f6393/6493/8393/8493 ds39896b-page 18 ? 2009 microchip technology inc. porte is a bidirectional i/o port. lcdbias1 lcdbias1 2 i analog bias1 input for lcd. lcdbias2 lcdbias2 1 i analog bias2 input for lcd. lcdbias3 lcdbias3 64 i analog bias3 input for lcd. com0 com0 63 o analog com0 output for lcd. re4/com1 re4 com1 62 i/o o st analog digital i/o. com1 output for lcd. re5/com2 re5 com2 61 i/o o st analog digital i/o. com2 output for lcd. re6/com3 re6 com3 60 i/o o st analog digital i/o. com3 output for lcd. re7/ccp2/seg31 re7 ccp2 (2) seg31 59 i/o i/o o st st analog digital i/o. capture 2 input/compare 2 output/pwm2 output. seg31 output for lcd. table 1-2: pic18f6x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39896b-page 19 pic18f6393/6493/8393/8493 portf is a bidirectional i/o port. rf0/an5/seg18 rf0 an5 seg18 18 i/o i o st analog analog digital i/o. analog input 5. seg18 output for lcd. rf1/an6/c2out/seg19 rf1 an6 c2out seg19 17 i/o i o o st analog ? analog digital i/o. analog input 6. comparator 2 output. seg19 output for lcd. rf2/an7/c1out/seg20 rf2 an7 c1out seg20 16 i/o i o o st analog ? analog digital i/o. analog input 7. comparator 1 output. seg20 output for lcd. rf3/an8/seg21 rf3 an8 seg21 15 i/o i o st analog analog digital i/o. analog input 8. seg21 output for lcd. rf4/an9/seg22 rf4 an9 seg22 14 i/o i o st analog analog digital i/o. analog input 9. seg22 output for lcd. rf5/an10/cv ref /seg23 rf5 an10 cv ref seg23 13 i/o i o o st analog analog analog digital i/o. analog input 10. comparator reference voltage output. seg23 output for lcd. rf6/an11/seg24 rf6 an11 seg24 12 i/o i o st analog analog digital i/o. analog input 11. seg24 output for lcd. rf7/ss /seg25 rf7 ss seg25 11 i/o i o st ttl analog digital i/o. spi? slave select input. seg25 output for lcd. table 1-2: pic18f6x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f6393/6493/8393/8493 ds39896b-page 20 ? 2009 microchip technology inc. portg is a bidirectional i/o port. rg0/seg30 rg0 seg30 3 i/o o st analog digital i/o. seg30 output for lcd. rg1/tx2/ck2/seg29 rg1 tx2 ck2 seg29 4 i/o o i/o o st ? st analog digital i/o. ausart2 asynchronous transmit. ausart2 synchronous clock (see related rx2/dt2). seg29 output for lcd. rg2/rx2/dt2/seg28 rg2 rx2 dt2 seg28 5 i/o i i/o o st st st analog digital i/o. ausart2 asynchronous receive. ausart2 synchronous data (see related tx2/ck2). seg28 output for lcd. rg3/seg27 rg3 seg27 6 i/o o st analog digital i/o. seg27 output for lcd. rg4/seg26 rg4 seg26 8 i/o o st analog digital i/o. seg26 output for lcd. rg5 see mclr /v pp /rg5 pin. v ss 9, 25, 41, 56 p ? ground reference for logic and i/o pins. v dd 10, 26, 38, 57 p ? positive supply for logic and i/o pins. av ss 20 p ? ground reference for analog modules. av dd 19 p ? positive supply for analog modules. table 1-2: pic18f6x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39896b-page 21 pic18f6393/6493/8393/8493 table 1-3: pic18f8x93 pi nout i/o descriptions pin name pin number pin type buffer type description tqfp mclr /v pp /rg5 mclr v pp rg5 9 i p i st st master clear (input) or programming voltage (input). master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. digital input. osc1/clki/ra7 osc1 clki ra7 49 i i i/o st cmos ttl oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode; cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 50 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f6393/6493/8393/8493 ds39896b-page 22 ? 2009 microchip technology inc. porta is a bidirectional i/o port. ra0/an0 ra0 an0 30 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 29 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref -/seg16 ra2 an2 v ref - seg16 28 i/o i i o ttl analog analog analog digital i/o. analog input 2. a/d reference voltage (low) input. seg16 output for lcd. ra3/an3/v ref +/seg17 ra3 an3 v ref + seg17 27 i/o i i o ttl analog analog analog digital i/o. analog input 3. a/d reference voltage (high) input. seg17 output for lcd. ra4/t0cki/seg14 ra4 t0cki seg14 34 i/o i o st/od st analog digital i/o. open-drain when configured as output. timer0 external clock input. seg14 output for lcd. ra5/an4/hlvdin/seg15 ra5 an4 hlvdin seg15 33 i/o i i o ttl analog analog analog digital i/o. analog input 4. low-voltage detect input. seg15 output for lcd. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. table 1-3: pic18f8x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39896b-page 23 pic18f6393/6493/8393/8493 portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0 rb0 int0 58 i/o i ttl st digital i/o. external interrupt 0. rb1/int1/seg8 rb1 int1 seg8 57 i/o i o ttl st analog digital i/o. external interrupt 1. seg8 output for lcd. rb2/int2/seg9 rb2 int2 seg9 56 i/o i o ttl st analog digital i/o. external interrupt 2. seg9 output for lcd. rb3/int3/seg10 rb3 int3 seg10 55 i/o i o ttl st analog digital i/o. external interrupt 3. seg10 output for lcd. rb4/kbi0/seg11 rb4 kbi0 seg11 54 i/o i o ttl ttl analog digital i/o. interrupt-on-change pin. seg11 output for lcd. rb5/kbi1 rb5 kbi1 53 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb6/kbi2/pgc rb6 kbi2 pgc 52 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 47 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-3: pic18f8x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f6393/6493/8393/8493 ds39896b-page 24 ? 2009 microchip technology inc. portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 36 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 (1) 35 i/o i i/o st cmos st digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm2 output. rc2/ccp1/seg13 rc2 ccp1 seg13 43 i/o i/o o st st analog digital i/o. capture 1 input/compare 1 output/pwm1 output. seg13 output for lcd. rc3/sck/scl rc3 sck scl 44 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi/sda rc4 sdi sda 45 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo/seg12 rc5 sdo seg12 46 i/o o o st ? analog digital i/o. spi data out. seg12 output for lcd. rc6/tx1/ck1 rc6 tx1 ck1 37 i/o o i/o st ? st digital i/o. eusart1 asynchronous transmit. eusart1 synchronous clock (see related rx1/dt1). rc7/rx1/dt1 rc7 rx1 dt1 38 i/o i i/o st st st digital i/o. eusart1 asynchronous receive. eusart1 synchronous data (see related tx1/ck1). table 1-3: pic18f8x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39896b-page 25 pic18f6393/6493/8393/8493 portd is a bidirectional i/o port. rd0/seg0 rd0 seg0 72 i/o o st analog digital i/o. seg0 output for lcd. rd1/seg1 rd1 seg1 69 i/o o st analog digital i/o. seg1 output for lcd. rd2/seg2 rd2 seg2 68 i/o o st analog digital i/o. seg2 output for lcd. rd3/seg3 rd3 seg3 67 i/o o st analog digital i/o. seg3 output for lcd. rd4/seg4 rd4 seg4 66 i/o o st analog digital i/o. seg4 output for lcd. rd5/seg5 rd5 seg5 65 i/o o st analog digital i/o. seg5 output for lcd. rd6/seg6 rd6 seg6 64 i/o o st analog digital i/o. seg6 output for lcd. rd7/seg7 rd7 seg7 63 i/o o st analog digital i/o. seg7 output for lcd. table 1-3: pic18f8x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f6393/6493/8393/8493 ds39896b-page 26 ? 2009 microchip technology inc. porte is a bidirectional i/o port. lcdbias1 lcdbias1 4 i analog bias1 input for lcd. lcdbias2 lcdbias2 3 i analog bias2 input for lcd. lcdbias3 lcdbias3 78 i analog bias3 input for lcd. com0 com0 77 o analog com0 output for lcd. re4/com1 re4 com1 76 i/o o st analog digital i/o. com1 output for lcd. re5/com2 re5 com2 75 i/o o st analog digital i/o. com2 output for lcd. re6/com3 re6 com3 74 i/o o st analog digital i/o. com3 output for lcd. re7/ccp2/seg31 re7 ccp2 (2) seg31 73 i/o i/o o st st analog digital i/o. capture 2 input/compare 2 output/pwm2 output. seg31 output for lcd. table 1-3: pic18f8x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39896b-page 27 pic18f6393/6493/8393/8493 portf is a bidirectional i/o port. rf0/an5/seg18 rf0 an5 seg18 24 i/o i o st analog analog digital i/o. analog input 5. seg18 output for lcd. rf1/an6/c2out/seg19 rf1 an6 c2out seg19 23 i/o i o o st analog ? analog digital i/o. analog input 6. comparator 2 output. seg19 output for lcd. rf2/an7/c1out/seg20 rf2 an7 c1out seg20 18 i/o i o o st analog ? analog digital i/o. analog input 7. comparator 1 output. seg20 output for lcd. rf3/an8/seg21 rf3 an8 seg21 17 i/o i o st analog analog digital i/o. analog input 8. seg21 output for lcd. rf4/an9/seg22 rf4 an9 seg22 16 i/o i o st analog analog digital i/o. analog input 9. seg22 output for lcd. rf5/an10/cv ref /seg23 rf5 an10 cv ref seg23 15 i/o i o o st analog analog analog digital i/o. analog input 10. comparator reference voltage output. seg23 output for lcd. rf6/an11/seg24 rf6 an11 seg24 14 i/o i o st analog analog digital i/o. analog input 11. seg24 output for lcd. rf7/ss /seg25 rf7 ss seg25 13 i/o i o st ttl analog digital i/o. spi slave select input. seg25 output for lcd. table 1-3: pic18f8x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f6393/6493/8393/8493 ds39896b-page 28 ? 2009 microchip technology inc. portg is a bidirectional i/o port. rg0/seg30 rg0 seg30 5 i/o o st analog digital i/o. seg30 output for lcd. rg1/tx2/ck2/seg29 rg1 tx2 ck2 seg29 6 i/o o i/o o st ? st analog digital i/o. ausart2 asynchronous transmit. ausart2 synchronous clock (see related rx2/dt2). seg29 output for lcd. rg2/rx2/dt2/seg28 rg2 rx2 dt2 seg28 7 i/o i i/o o st st st analog digital i/o. ausart2 asynchronous receive. ausart2 synchronous data (see related tx2/ck2). seg28 output for lcd. rg3/seg27 rg3 seg27 8 i/o o st analog digital i/o. seg27 output for lcd. rg4/seg26 rg4 seg26 10 i/o o st analog digital i/o. seg26 output for lcd. rg5 see mclr /v pp /rg5 pin. table 1-3: pic18f8x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39896b-page 29 pic18f6393/6493/8393/8493 porth is a bidirectional i/o port. rh0/seg47 rh0 seg47 79 i/o o st analog digital i/o. seg47 output for lcd. rh1/seg46 rh1 seg46 80 i/o o st analog digital i/o. seg46 output for lcd. rh2/seg45 rh2 seg45 1 i/o o st analog digital i/o. seg45 output for lcd. rh3/seg44 rh3 seg44 2 i/o o st analog digital i/o. seg44 output for lcd. rh4/seg40 rh4 seg40 22 i/o o st analog digital i/o. seg40 output for lcd. rh5/seg41 rh5 seg41 21 i/o o st analog digital i/o. seg41 output for lcd. rh6/seg42 rh6 seg42 20 i/o o st analog digital i/o. seg42 output for lcd. rh7/seg43 rh7 seg43 19 i/o o st analog digital i/o. seg43 output for lcd. table 1-3: pic18f8x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
pic18f6393/6493/8393/8493 ds39896b-page 30 ? 2009 microchip technology inc. portj is a bidirectional i/o port. rj0/seg32 rj0 seg32 62 i/o o st analog digital i/o. seg32 output for lcd. rj1/seg33 rj1 seg33 61 i/o o st analog digital i/o. seg33 output for lcd. rj2/seg34 rj2 seg34 60 i/o o st analog digital i/o. seg34 output for lcd. rj3/seg35 rj3 seg35 59 i/o o st analog digital i/o. seg35 output for lcd. rj4/seg39 rj4 seg39 39 i/o o st analog digital i/o. seg39 output for lcd. rj5/seg38 rj5 seg38 40 i/o o st analog digital i/o seg38 output for lcd. rj6/seg37 rj6 seg37 41 i/o o st analog digital i/o. seg37 output for lcd. rj7/seg36 rj7 seg36 42 i/o o st analog digital i/o. seg36 output for lcd. v ss 11, 31, 51, 70 p ? ground reference for logic and i/o pins. v dd 12, 32, 48, 71 p ? positive supply for logic and i/o pins. av ss 26 p ? ground reference for analog modules. av dd 25 p ? positive supply for analog modules. table 1-3: pic18f8x93 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for ccp2 when configuration bit, ccp2mx, is cleared.
? 2009 microchip technology inc. ds39896b-page 31 pic18f6393/6493/8393/8493 2.0 12-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module converts an analog input signal to a 12-bit digital number. the module has 12 inputs for both pic18f6393/6493 (64-pin) and pic18f8393/8493 (80-pin) devices. the module has five registers: ? a/d result high register (adresh) ? a/d result low register (adresl) ? a/d control register 0 (adcon0) ? a/d control register 1 (adcon1) ? a/d control register 2 (adcon2) the adcon0 register, shown in register 2-1, controls the operation of the a/d module. the adcon1 register, shown in register 2-2, configures the functions of the port pins. the adcon2 register, shown in register 2-3, configures the a/d clock source, programmed acquisition time and justification. register 2-1: adcon0: a/ d control register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-2 chs3:chs0: analog channel select bits 0000 = channel 0 (an0) 0001 = channel 1 (an1) 0010 = channel 2 (an2) 0011 = channel 3 (an3) 0100 = channel 4 (an4) 0101 = channel 5 (an5) 0110 = channel 6 (an6) 0111 = channel 7 (an7) 1000 = channel 8 (an8) 1001 = channel 9 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 1100 = unimplemented (1) 1101 = unimplemented (1) 1110 = unimplemented (1) 1111 = unimplemented (1) bit 1 go/done : a/d conversion status bit when adon = 1 : 1 = a/d conversion in progress 0 = a/d idle bit 0 adon: a/d on bit 1 = a/d converter module is enabled 0 = a/d converter module is disabled note 1: performing a conversion on unimplemented channels will return a floating input measurement.
pic18f6393/6493/8393/8493 ds39896b-page 32 ? 2009 microchip technology inc. register 2-2: adcon1: a/ d control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-4 vcfg1:vcfg0: voltage reference configuration bits bit 3-0 pcfg3:pcfg0: a/d port configuration control bits a/d v ref + a/d v ref - 00 av dd av ss 01 external v ref +av ss 10 av dd external v ref - 11 external v ref + external v ref - a = analog input d = digital i/o pcfg<3:0> an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 0000 aaaaaaaaaaaa 0001 aaaaaaaaaaaa 0010 aaaaaaaaaaaa 0011 aaaaaaaaaaaa 0100 d aaa a a aaaaaa 0101 ddaa a a aaaaaa 0110 dddaaaaaaaaa 0111 dddd a a aaaaaa 1000 ddddd a aaaaaa 1001 ddddddaaaaaa 1010 dddddddaaaaa 1011 ddddddddaaaa 1100 dddddddddaaa 1101 ddddddddddaa 1110 ddddddddddda 1111 dddddddddddd
? 2009 microchip technology inc. ds39896b-page 33 pic18f6393/6493/8393/8493 register 2-3: adcon2: a/ d control register 2 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6 unimplemented: read as ? 0 ? bit 5-3 acqt2:acqt0: a/d acquisition time select bits 111 = 20 t ad 110 = 16 t ad 101 = 12 t ad 100 = 8 t ad 011 = 6 t ad 010 = 4 t ad 001 = 2 t ad 000 = 0 t ad (1) bit 2-0 adcs2:adcs0: a/d conversion clock select bits 111 = f rc (clock derived from a/d rc oscillator) (1) 110 = f osc /64 101 = f osc /16 100 = f osc /4 011 = f rc (clock derived from a/d rc oscillator) (1) 010 = f osc /32 001 = f osc /8 000 = f osc /2 note 1: if the a/d f rc clock source is selected, a delay of one t cy (instruction cycle) is added before the a/d clock starts. this allows the sleep instruction to be executed before starting a conversion.
pic18f6393/6493/8393/8493 ds39896b-page 34 ? 2009 microchip technology inc. the analog reference voltage is software selectable to either the device?s positive and negative supply voltage (v dd and v ss ), or the voltage level on the ra3/an3/ v ref +/seg17 and ra2/an2/v ref -/seg16 pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion in progress is aborted. each port pin associated with the a/d converter can be configured as an analog input or a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is com- plete, the result is loaded into the adresh:adresl register pair, the go/done bit (adcon0<1>) is cleared and the a/d interrupt flag bit, adif, is set. the block diagram of the a/d module is shown in figure 2-1. figure 2-1: a/d block diagram (input voltage) v ain v ref + reference voltage av dd (1) vcfg1:vcfg0 chs3:chs0 an7 an6 an5 an4 an3 an2 an1 an0 0111 0110 0101 0100 0011 0010 0001 0000 12-bit a/d v ref - av ss (1) converter an11 an10 an9 an8 1011 1010 1001 1000 note 1: i/o pins have diode protection to v dd and v ss . 0 x 1 x x 1 x 0
? 2009 microchip technology inc. ds39896b-page 35 pic18f6393/6493/8393/8493 the value in the adresh:adresl registers is unknown following power-on and brown-out resets and is not affected by any other reset. after the a/d module has been configured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 2.1 ?a/d acquisition requirements? . after this acquisi- tion time has elapsed, the a/d conversion can be started. an acquisition time can be programmed to occur between setting the go/done bit and the actual start of the conversion. the following steps should be followed to perform an a/d conversion: 1. configure the a/d module: ? configure analog pins, voltage reference and digital i/o (adcon1) ? select a/d input channel (adcon0) ? select a/d acquisition time (adcon2) ? select a/d conversion clock (adcon2) ? turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): ? clear adif bit ? set adie bit ? set gie bit 3. wait the required acquisition time (if required). 4. start conversion: ? set go/done bit (adcon0<1>) 5. wait for a/d conversion to complete by either: ? polling for the go/done bit to be cleared or ? waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear bit, adif, if required. 7. for the next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before the next acquisition starts. figure 2-2: a/d transfer function figure 2-3: analog input model digital code output ffeh 003h 002h 001h 000h 0.5 lsb 1 lsb 1.5 lsb 2 lsb 2.5 lsb 4094 lsb 4094.5 lsb 3 lsb analog input voltage fffh 4095 lsb 4095.5 lsb v ain c pin rs anx 5 pf v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 25 pf v ss v dd 100 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions = sampling switch resistance r ss v dd 6v sampling switch 5v 4v 3v 2v 123 4 (k )
pic18f6393/6493/8393/8493 ds39896b-page 36 ? 2009 microchip technology inc. 2.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 2-3. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor, c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the ana- log input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k . after the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. to calculate the minimum acquisition time, equation 2-1 may be used. this equation assumes that 1/2 lsb error is used (4096 steps for the 12-bit a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. equation 2-3 shows the calculation of the minimum required acquisition time, t acq . this calculation is based on the following application system assumptions: c hold = 25 pf rs = 2.5 k conversion error 1/2 lsb v dd =3v rss = 4 k temperature = 85 c (system max.) equation 2-1: acquisition time equation 2-2: a/d minimum charging time equation 2-3: calculating the minimum required acquisition time note: when the conversion is started, the holding capacitor is disconnected from the input pin. t acq = amplifier settling time + holding capacitor charging time + temperature coefficient =t amp + t c + t coff v hold = (v ref ? (v ref /4096)) ? (1 ? e (-t c /c hold (r ic + r ss + r s )) ) or t c = ? (c hold )(r ic + r ss + r s ) ln(1/4096) t acq =t amp + t c + t coff t amp =0.2 s t coff = (temp ? 25 c)(0.02 s/ c) (85 c ? 25 c)(0.02 s/ c) 1.2 s temperature coefficient is only required for temperatures > 25 c. below 25 c, t coff = 0 s. t c = -(c hold )(r ic + r ss + r s ) ln(1/4096) s -(25 pf) (1 k + 4 k + 2.5 k ) ln(0.0002441) s 1.56 s t acq = 0.2 s + 1.56 s + 1.2 s 2.96 s
? 2009 microchip technology inc. ds39896b-page 37 pic18f6393/6493/8393/8493 2.2 selecting and configuring acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. it also gives users the option to use an automatically determined acquisition time. acquisition time may be set with the acqt2:acqt0 bits (adcon2<5:3>), which provide a range of 2 to 20 t ad . when the go/done bit is set, the a/d module continues to sample the input for the selected acquisi- tion time, then automatically begins a conversion. since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the go/done bit. manual acquisition is selected when acqt2:acqt0 = 000 . when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this option is also the default reset state of the acqt2:acqt0 bits and is compatible with devices that do not offer programmable acquisition times. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/d begins sampling the currently selected channel again. if an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 2.3 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 13 t ad per 12-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : ?2 t osc ?4 t osc ?8 t osc ?16 t osc ?32 t osc ?64 t osc ? internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be as short as possible, but greater than the minimum t ad . (see parameter 130 for more information.) table 2-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 2-1: t ad vs. device operating frequencies a/d clock source (t ad ) assumes t ad min. = 0.8 s operation adcs2:adcs0 maximum f osc 2 t osc 000 2.50 mhz 4 t osc 100 5.00 mhz 8 t osc 001 10.00 mhz 16 t osc 101 20.00 mhz 32 t osc 010 40.00 mhz 64 t osc 110 40.00 mhz rc (1) x11 1.00 mhz (2) note 1: the rc source has a typical t ad time of 2.5 s. 2: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion or a f osc divider should be used instead; otherwise, the a/d accuracy specification may not be met.
pic18f6393/6493/8393/8493 ds39896b-page 38 ? 2009 microchip technology inc. 2.4 operation in power-managed modes the selection of the automatic acquisition time and a/d conversion clock is determined in part by the clock source and frequency while in a power-managed mode. if the a/d is expected to operate while the device is in a power-managed mode, the adcs2:adcs0 bits in adcon2 should be updated in accordance with the clock source to be used. the acqt2:acqt0 bits do not need to be adjusted as the adcs2:adcs0 bits adjust the t ad time for the new clock speed. after enter- ing the mode, an a/d acquisition or conversion may be started. once started, the device should continue to be clocked by the same clock source until the conversion has been completed. if desired, the device may be placed into the corresponding idle mode during the conversion. if the device clock frequency is less than 1 mhz, the a/d rc clock source should be selected. operation in sleep mode requires the a/d f rc clock to be selected. if the acqt2:acqt0 bits are set to ? 000 ? and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the sleep instruction and entry to sleep mode. the idlen bit (osccon<7>) must have already been cleared prior to starting the conversion. 2.5 configuring analog port pins the adcon1, trisa, trisf and trish registers all configure the a/d port pins. the port pins needed as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs3:chs0 bits and the tris bits. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). analog con- version on pins configured as digital pins can be performed. the voltage on the pin will be accurately converted. 2: analog levels on any pin defined as a dig- ital input may cause the digital input buffer to consume current out of the device?s specification limits.
? 2009 microchip technology inc. ds39896b-page 39 pic18f6393/6493/8393/8493 2.6 a/d conversions figure 2-4 shows the operation of the a/d converter after the go/done bit has been set and the acqt2:acqt0 bits are cleared. a conversion is started after the following instruction to allow entry into sleep mode before the conversion begins. figure 2-5 shows the operation of the a/d converter after the go/done bit has been set, the acqt2:acqt0 bits are set to ? 010 ? and a 4 t ad acqui- sition time has been selected before the conversion starts. clearing the go/done bit during a conversion will abort the current conversion. the a/ d result register pair will not be updated with the partially completed a/d conversion sample. this means the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is completed or aborted, a 2t ad wait is required before the next acquisition can be started. after this wait, acquisition on the selected channel is automatically started. 2.7 discharge the discharge phase is used to initialize the value of the holding capacitor. the array is discharged before every sample. this feature helps to optimize the unity gain amplifier, as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous-measure values. figure 2-4: a/d conversion t ad cycles (acqt<2:0> = 000 , t acq = 0 ) figure 2-5: a/d conversion t ad cycles (acqt<2:0> = 010 , t acq = 4 t ad ) note: the go/done bit should not be set in the same instruction that turns on the a/d. code should wait at least 2 s after enabling the a/d before beginning an acquisition and conversion cycle. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go/done bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy ? t ad adresh:adresl are loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input conversion starts b2 b11 b8 b7 b6 b5 b4 b3 b10 b9 on the following cycle: discharge t ad 13 t ad 12 b0 b1 t ad 1 (typically 200 ns) 1 2 3 4 5 6 7 8 13 set go/done bit (holding capacitor is disconnected) 9 12 conversion starts 1 2 3 4 (holding capacitor continues acquiring input) t acqt cycles t ad cycles automatic acquisition time b0 b11 b8 b7 b6 b5 b4 b1 b10 b9 adresh:adresl are loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input on the following cycle: t ad 1 discharge 10 11 b3 b2 (typically 200 ns)
pic18f6393/6493/8393/8493 ds39896b-page 40 ? 2009 microchip technology inc. 2.8 use of the eccp2 trigger an a/d conversion can be started by the special event trigger of the eccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be programmed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d acquisition and conversion, and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to automat- ically repeat the a/d acquisition period with minimal software overhead (moving adresh:adresl to the desired location). the appropriate analog input chan- nel must be selected and the minimum acquisition period is either timed by the user, or an appropriate t acq time selected before the special event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the special event trigger will be ignored by the a/d module but will still reset the timer1 (or timer3) counter. table 2-2: registers associated with a/d operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif (3) pir1 ?adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if (3) pie1 ?adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie (3) ipr1 ?adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip (3) pir2 oscfif cmif ? ? bcl1if hlvdif tmr3if ccp2if (3) pie2 oscfie cmie ? ? bcl1ie hlvdie tmr3ie ccp2ie (3) ipr2 oscfip cmip ? ? bcl1ip hlvdip tmr3ip ccp2ip (3) adresh a/d result register high byte (3) adresl a/d result register low byte (3) adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon (3) adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 (3) adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 (3) trisa trisa7 (1) trisa6 (1) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 (3) trisf trisf7 trisf6 trisf5 trisf 4 trisf3 trisf2 trisf1 trisf0 (3) trish (2) trish7 trish6 trish5 trish4 trish3 trish2 trish1 trish0 (3) legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for a/d conversion. note 1: porta<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. when disabled, these bits read as ? 0 ?. 2: these registers are not implemented on 64-pin devices. 3: for these reset values, see the ? pic18f6390/6490/8390/8490 data sheet? (ds39629).
? 2009 microchip technology inc. ds39896b-page 41 pic18f6393/6493/8393/8493 3.0 special features of the cpu pic18f6393/6493/8393/8493 devices include several features intended to maximize reliability and minimize cost through elimination of external components. these include: ? device id registers 3.1 device id registers the device id registers are ?read-only? registers. they identify the device type and revision to device programmers and can be read by firmware using table reads. table 3-1: device ids note: for additional details on the configuration bits, refer to section 23.1 ?configuration bits? in the ? pic18f6390/6490/8390/8490 data sheet? (ds39629). device id informa- tion presented in this section is for the pic18f6393/6493/8393/8493 devices only. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 xxxx xxxx (1) 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 xxxx xxxx (1) legend: x = unknown note 1: see register 3-1 and register 3-2 for devid values. devid r egisters are read-only and cannot be programmed by the user.
pic18f6393/6493/8393/8493 ds39896b-page 42 ? 2009 microchip technology inc. register 3-1: devid1: device id register 1 for pic18f6393/6493/8393/8493 devices rrrrrrrr dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state bit 7-5 dev2:dev0: device id bits see register 3-2 for a complete listing. bit 4-0 rev4:rev0: revision id bits these bits are used to indicate the device revision. register 3-2: devid2: device id register 2 for pic18f6393/6493/8393/8493 devices rrrrrrrr dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 bit 7 bit 0 legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state bit 7-0 dev10:dev3: device id bits device dev10:dev3 (devid2<7:0>) dev2:dev0 (devid1<7:5>) pic18f6393 0001 1010 000 PIC18F6493 0000 1110 000 pic18f8393 0001 1010 001 pic18f8493 0000 1110 001
? 2009 microchip technology inc. ds39896b-page 43 pic18f6393/6493/8393/8493 4.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd and mclr ) ................................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ......................................................................................... 0v to +13.25v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ............................................................... ....................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................... ............................................... 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports ...................................................................................................................... .200 ma maximum current sourced by all ports ........................................................................................... .......................200 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v ol x i ol ) 2: voltage spikes below v ss at the mclr /v pp /rg5 pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 should be used when applying a ?low? level to the mclr /v pp / rg5 pin, rather than pulling this pin directly to v ss . note: other than some basic data, this section documents only the pic18f6393/6493/8393/8493 devices? specifica- tions that differ from those of the pic18f6390/6490/8390/8490 devices. for detailed information on the electrical specifications shared by the pic18f6393/6493/8393/8493 and pic18f6390/6490/8390/8490 devices, see the ? pic18f6390/6490/8390/8490 data sheet? (ds39629). ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic18f6393/6493/8393/8493 ds39896b-page 44 ? 2009 microchip technology inc. figure 4-1: pic18f6393/6493/8393/8493 voltage-frequency graph (industrial) figure 4-2: pic18lf6393/6493/8393/8493 voltage-frequency graph (industrial) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 40 mhz 5.0v 3.5v 3.0v 2.5v pic18fx393/x493 4.2v frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 40 mhz 5.0v 3.5v 3.0v 2.5v pic18lfx393/x493 f max = (16.36 mhz/v) (v ddappmin ? 2.0v) + 4 mhz note: v ddappmin is the minimum voltage of the pic ? device in the application. 4 mhz 4.2v
? 2009 microchip technology inc. ds39896b-page 45 pic18f6393/6493/8393/8493 table 4-1: a/d converter characteristics: pic18f6393/6493/8393/8493 (industrial) param no. sym characteristic min typ max units conditions a01 n r resolution ? ? 12 bit v ref 3.0v a03 e il integral linearity error ? <1 2.0 lsb v dd = 3.0v v ref 3.0v ??2.0lsbv dd = 5.0v a04 e dl differential linearity error ? <1 +1.5/-1.0 lsb v dd = 3.0v v ref 3.0v ??+1.5/-1.0lsbv dd = 5.0v a06 e off offset error ? <1 5 lsb v dd = 3.0v v ref 3.0v ??3lsbv dd = 5.0v a07 e gn gain error ? <1 2.00 lsb v dd = 3.0v v ref 3.0v ??2.00lsbv dd = 5.0v a10 ? monotonicity guaranteed (1) ?v ss v ain v ref a20 v ref reference voltage range (v refh ? v refl ) 3?v dd ? v ss v for 12-bit resolution a21 v refh reference voltage high v ss + 3.0v ? v dd + 0.3v v for 12-bit resolution a22 v refl reference voltage low v ss ? 0.3v ? v dd ? 3.0v v for 12-bit resolution a25 v ain analog input voltage v refl ?v refh v a30 z ain recommended impedance of analog voltage source ??2.5k a50 i ref v ref input current (2) ? ? ? ? 5 150 a a during v ain acquisition. during a/d conversion cycle. note 1: the a/d conversion result never decreases with an in crease in the input voltage and has no missing codes. 2: v refh current is from the ra3/an3/v ref +/seg17 pin or v dd , whichever is selected as the v refh source. v refl current is from the ra2/an2/v ref -/seg16 pin or v ss , whichever is selected as the v refl source.
pic18f6393/6493/8393/8493 ds39896b-page 46 ? 2009 microchip technology inc. figure 4-3: a/d conversion timing table 4-2: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk (1) a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 11 10 9 3 2 1 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . t cy 0 param no. symbol characteristic min max units conditions 130 t ad a/d clock period pic18 f xxxx 0.8 12.5 (1) st osc based, v ref 3.0v pic18 lf xxxx 1.4 25.0 (1) sv dd = 3.0v; t osc based, v ref full range pic18 f xxxx ? 1 s a/d rc mode pic18 lf xxxx ? 3 sv dd = 3.0v; a/d rc mode 131 t cnv conversion time (not including acquisition time) (2) 13 14 t ad 132 t acq acquisition time (3) 1.4 ? s 135 t swc switching time from convert sample ? (note 4) 137 t dis discharge time 0.2 ? s note 1: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. 2: adres registers may be read on the following t cy cycle. 3: the time for the holding capacitor to acquire the ?new? input voltage when the voltage changes full scale after the conversion (v dd to v ss or v ss to v dd ). the source impedance (r s ) on the input channels is 50 . 4: on the following cycle of the device clock.
? 2009 microchip technology inc. ds39896b-page 47 pic18f6393/6493/8393/8493 5.0 packaging information for packaging information, see the ? pic18f6390/6490/ 8390/8490 data sheet? (ds39629).
pic18f6393/6493/8393/8493 ds39896b-page 48 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds39896b-page 49 pic18f6393/6493/8393/8493 appendix a: revision history revision a (september 2007) original data sheet for the pic18f6393/6493/8393/ 8493 devices. revision b (october 2009) removed ?preliminary? marking. appendix b: device differences the differences between the devices listed in this data sheet are shown in table b-1. table b-1: device differences features pic18f6393 PIC18F6493 pic18f8393 pic18f8493 number of pixels the lcd driver can drive 128 (4 x 32) 128 (4 x 32) 192 (4 x 48) 192 (4 x 48) i/o ports ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g, h, j ports a, b, c, d, e, f, g, h, j flash program memory 8 kbytes 16 kbytes 8 kbytes 16 kbytes packages 64-pin tqfp 64-pin tqfp 80-pin tqfp 80-pin tqfp
pic18f6393/6493/8393/8493 ds39896b-page 50 ? 2009 microchip technology inc. appendix c: conversion considerations this appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. typically, these changes are due to the differences in the process technology used. an example of this type of conversion is from a pic16c74a to a pic16c74b. not applicable appendix d: migration from baseline to enhanced devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to an enhanced mcu device (i.e., pic18fxxx). the following are the list of modifications over the pic16c5x microcontroller family: not currently available
? 2009 microchip technology inc. ds39896b-page 51 pic18f6393/6493/8393/8493 appendix e: migration from mid-range to enhanced devices a detailed discussion of the differences between the mid-range mcu devices (i.e., pic16cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an716, ?migrating designs from pic16c74a/74b to pic18c442? . the changes discussed, while device- specific, are generally applicable to all mid-range to enhanced device migrations. this application note is available as literature number ds00716. appendix f: migration from high-end to enhanced devices a detailed discussion of the migration pathway and differences between the high-end mcu devices (i.e., pic17cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an726, ?pic17cxxx to pic18cxxx migration? . this application note is available as literature number ds00726.
pic18f6393/6493/8393/8493 ds39896b-page 52 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds39896b-page 53 pic18f6393/6493/8393/8493 index a a/d ...................................................................................... 31 a/d converter interrupt, configuring .......................... 35 acquisition requirements ........................................... 36 adcon0 register....................................................... 31 adcon1 register....................................................... 31 adcon2 register....................................................... 31 adresh register................................................. 31, 34 adresl register ....................................................... 31 analog port pins, configuring..................................... 38 associated registers .................................................. 40 configuring the module............................................... 35 conversion clock (t ad ) .............................................. 37 conversion requirements .......................................... 46 conversion status (go/done bit) ............................. 34 conversions ................................................................ 39 converter characteristics ........................................... 45 discharge.................................................................... 39 operation in power-managed modes ......................... 38 selecting and configuring acquisition time ............... 37 special event trigger (eccp2) .................................. 40 transfer function........................................................ 35 use of the eccp2 trigger .......................................... 40 absolute maximum ratings ................................................ 43 adcon0 register............................................................... 31 go/done bit.............................................................. 34 adcon1 register............................................................... 31 adcon2 register............................................................... 31 adresh register............................................................... 31 adresl register ......................................................... 31, 34 analog-to-digital converter. see a/d. b block diagrams a/d .............................................................................. 34 analog input model ..................................................... 35 pic18f6x93 ............................................................... 11 pic18f8x93 ............................................................... 12 c compare (eccp2 module) special event trigger.................................................. 40 conversion considerations ................................................. 50 customer change notification service ............................... 55 customer notification service............................................. 55 customer support............................................................... 55 d device differences.............................................................. 49 device id registers ............................................................ 41 device overview ................................................................... 9 details of individual devices ......................................... 9 features (table)........................................................... 10 special features ........................................................... 9 documentation most current versions .................................................. 7 related data sheet....................................................... 9 e electrical characteristics..................................................... 43 a/d converter ............................................................. 45 absolute maximum ratings ........................................ 43 low-power voltage-frequency graph........................ 44 voltage-frequency graph .......................................... 44 equations a/d acquisition time .................................................. 36 a/d minimum charging time ..................................... 36 calculating the minimum required acquisition time . 36 errata .................................................................................... 7 i internet address ................................................................. 55 interrupt sources a/d conversion complete .......................................... 35 l lcd driver features ....................................................................... 3 m microchip internet web site................................................ 55 microcontroller special features........................................................... 3 migration from baseline to enhanced devices ................... 50 migration from high-end to enhanced devices.................. 51 migration from mid-range to enhanced devices ............... 51 o oscillator structure features ....................................................................... 3 p packaging information.................................................................. 47 peripheral highlights............................................................. 3 pin diagrams 64-pin tqfp................................................................. 4 80-pin tqfp................................................................. 5 pin functions av dd ........................................................................... 20 av dd ........................................................................... 30 av ss ........................................................................... 20 av ss ........................................................................... 30 com0 ................................................................... 18, 26 lcdbias1 ............................................................ 18, 26 lcdbias2 ............................................................ 18, 26 lcdbias3 ............................................................ 18, 26 mclr /v pp /rg5.................................................... 13, 21 osc1/clki/ra7................................................... 13, 21 osc2/clko/ra6 ................................................. 13, 21 ra0/an0............................................................... 14, 22 ra1/an1............................................................... 14, 22 ra2/an2/v ref -/seg16........................................ 14, 22 ra3/an3/v ref +/seg17....................................... 14, 22 ra4/t0cki/seg14............................................... 14, 22 ra5/an4/hlvdin/seg15 .................................... 14, 22 rb0/int0.............................................................. 15, 23 rb1/int1/seg8 ................................................... 15, 23 rb2/int2/seg9 ................................................... 15, 23 rb3/int3/seg10 ................................................. 15, 23 rb4/kbi0/seg11 ................................................. 15, 23 rb5/kbi1.............................................................. 15, 23 rb6/kbi2/pgc ..................................................... 15, 23 rb7/kbi3/pgd ..................................................... 15, 23 rc0/t1oso/t13cki ............................................ 16, 24 rc1/t1osi/ccp2 ................................................ 16, 24 rc2/ccp1/seg13 ............................................... 16, 24
pic18f6393/6493/8393/8493 ds39896b-page 54 ? 2009 microchip technology inc. rc3/sck/scl ...................................................... 16, 24 rc4/sdi/sda ....................................................... 16, 24 rc5/sdo/seg12 ................................................. 16, 24 rc6/tx1/ck1 ....................................................... 16, 24 rc7/rx1/dt1 ....................................................... 16, 24 rd0/seg0 ............................................................ 17, 25 rd0/seg1 .................................................................. 17 rd1/seg1 .................................................................. 25 rd2/seg2 ............................................................ 17, 25 rd3/seg3 ............................................................ 17, 25 rd4/seg4 ............................................................ 17, 25 rd5/seg5 ............................................................ 17, 25 rd6/seg6 ............................................................ 17, 25 rd7/seg7 ............................................................ 17, 25 re4/com1............................................................ 18, 26 re5/com2............................................................ 18, 26 re6/com3............................................................ 18, 26 re7/ccp2/seg31 ................................................ 18, 26 rf0/an5/seg18................................................... 19, 27 rf1/an6/c2out/seg19 ..................................... 19, 27 rf2/an7/c1out/seg20 ..................................... 19, 27 rf3/an8/seg21................................................... 19, 27 rf4/an9/seg22................................................... 19, 27 rf5/an10/cv ref /seg23 ..................................... 19, 27 rf6/an11/seg24................................................. 19, 27 rf7/ss /seg25 ..................................................... 19, 27 rg0/seg30 .......................................................... 20, 28 rg1/tx2/ck2/seg29 .......................................... 20, 28 rg2/rx2/dt2/seg28 .......................................... 20, 28 rg3/seg27 .......................................................... 20, 28 rg4/seg26 .......................................................... 20, 28 rg5....................................................................... 20, 28 rh0/seg47 ................................................................ 29 rh1/seg46 ................................................................ 29 rh2/seg45 ................................................................ 29 rh3/seg44 ................................................................ 29 rh4/seg40 ................................................................ 29 rh5/seg41 ................................................................ 29 rh6/seg42 ................................................................ 29 rh7/seg43 ................................................................ 29 rj0/seg32 ................................................................. 30 rj1/seg33 ................................................................. 30 rj2/seg34 ................................................................. 30 rj3/seg35 ................................................................. 30 rj4/seg39 ................................................................. 30 rj5/seg38 ................................................................. 30 rj6/seg37 ................................................................. 30 rj7/seg36 ................................................................. 30 v dd .............................................................................. 20 v dd .............................................................................. 30 v ss .............................................................................. 20 v ss .............................................................................. 30 pinout i/o descriptions pic18f6x93 ............................................................... 13 pic18f8x93 ............................................................... 21 power-managed modes and a/d operation ...................................................... 38 features ........................................................................ 3 product identification system.............................................. 57 r reader response ............................................................... 56 registers adcon0 (a/d control 0) ............................................ 31 adcon1 (a/d control 1) ............................................ 32 adcon2 (a/d control 2) ............................................ 33 devid1 (device id 1)................................................. 42 devid2 (device id 2)................................................. 42 revision history.................................................................. 49 s special features of the cpu .............................................. 41 device id registers .................................................... 41 t timing diagrams a/d conversion........................................................... 46 w www address ................................................................... 55 www, on-line support ......... .............................................. 7
? 2009 microchip technology inc. ds39896b-page 55 pic18f6393/6493/8393/8493 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
pic18f6393/6493/8393/8493 ds39896b-page 56 ? 2009 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39896b pic18f6393/6493/8393/8493 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2009 microchip technology inc. ds39896b-page 57 pic18f6393/6493/8393/8493 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device (1), (2) pic18f6393, PIC18F6493, pic18f8393, pic18f8493 ? v dd range: 4.2v to 5.5v pic18lf6393, pic18lf6493, pic18lf8393, pic18lf8493 ? v dd range: 2.0v to 5.5v temperature range i = -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package pt = tqfp (thin quad flatpack) pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18lf6393-i/pt 301 = industrial temp., tqfp package, extended v dd limits, qtp pattern #301. b) pic18lf6393-i/pt = industrial temp., tqfp package, extended v dd limits. c) pic18f6393-e/pt = extended temp., tqfp package, normal v dd limits. note 1: f = standard voltage range lf = wide voltage range 2: t = in tape and reel tqfp packages only.
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